Mentor Graphics and Xilinx to Develop Co-Verification Solutions for Xilinx Virtex-II Pro

WILSONVILLE, Ore. & SAN JOSE, Calif.--(BUSINESS WIRE)--July 22, 2002--Mentor Graphics Corporation (Nasdaq:MENT - News) and Xilinx, Inc. (Nasdaq:XLNX - News) today announced an agreement to develop a customized extension to the market-leading Seamless® co-verification environment, optimized to the needs of designers using the Xilinx® Virtex-II Pro(TM) Platform FPGA devices.

Under the terms of this agreement, Mentor Graphics and Xilinx will tailor a co-verification solution to the requirements of designers embedding the PowerPC 405 Core into Virtex-II Pro devices. The collaboration result will be a co-verification solution optimized for Xilinx FPGAs that will significantly ease the adoption of co-verification technology into the Xilinx design flows.

The Seamless Virtex-II Pro solution builds upon the existing Seamless co-verification environment and the production-proven, general-purpose PowerPC 405 Seamless processor support package (PSP). Encapsulating knowledge of the Virtex-II Pro devices within this co-verification solution significantly reduces integration time, enabling designers to be more productive in a shorter amount of time.

"Platform FPGAs with powerful embedded cores afford designers a level of integration not possible with previous generations of programmable devices," said Serge Leef, general manager of the System-on-Chip Verification Division at Mentor Graphics. "As designers adopt this methodology they will face some of the same verification challenges associated with ASIC/SoC design. Seamless has proven time and again a valuable solution in simplifying and speeding this process."

Programmable Systems Deliver Rich Feature Set with Integrated Processor Performance

Embedding processor cores into programmable devices increases the complexity of verifying such devices. The Seamless Virtex-II Pro solution addresses these issues and simplifies the process of designing with programmable systems even further by providing designers with a virtual prototype of the platform FPGA weeks or months ahead of the time when the first physical prototypes can be programmed.

Critical to the success of verifying a complex embedded device is the ability to control and visualize the operation of the system during the debug phase. Seamless co-verification encompasses the logic simulation and software debug tools already in use in system design and verification. Access to these tools within a virtual environment gives a level of control and observability not achievable with physical devices, not only for pre-silicon debug, but also for improved visibility when analyzing problems encountered on physical prototypes.

"Xilinx is committed to providing our customers with a comprehensive debug and verification strategy to adequately address the increased system-level capability of Virtex-II Pro based designs," said Rich Sevcik, senior vice president of FPGA products at Xilinx. "As part of our overall strategy we are pleased to work with Mentor in providing our customers with support for Seamless, a proven ASIC strength co-verification tool."

The Platform FPGA will be part of a complex system that will also require verification. Often this system will contain other processors and digital signal processors (DSPs). Seamless offers the most comprehensive range of processor models with support for all popular embedded architectures, making Seamless the solution for both the system and device verification.

Pricing and Availability

Seamless and the PowerPC(TM) 405 PSP are available now on Solaris, HP/UX, Linux and AIX platforms. The custom Seamless package for Xilinx Virtex-II Pro users includes the complete Seamless co-verification system, the PPC405 PSP and the Virtex-II Pro IP modules and memories. This package will be available in Q4 2002, under special one-year term licensing arrangements starting at $24,000. For more information, including pricing, or to register for free Seamless workshops and SoC verification seminars, visit our Web site at www.mentor.com/seamless.

About Seamless

Combining the best in embedded software development tools with logic simulation, the Mentor Graphics® Seamless co-verification environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be carried out in parallel removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as RTOS initialization, block memory transfers, and algorithmic routines. Seamless with the C-Bridge(TM) tool further boosts performance through incorporation of C hardware descriptions. Seamless supports all popular logic simulators and software development environments, including the Model Technology® ModelSim® environment.

About the Virtex-II Pro Family

The Xilinx Virtex-II Pro FPGA family is the world's first FPGA to immerse high-performance IBM PowerPC processors in the Virtex-II fabric with multi-gigabit serial transceivers to solve high-performance architectural challenges. Using its patent-pending IP Immersion(TM) technology, Xilinx has integrated these two essential requirements for next-generation systems, RISC processing and high-speed serial technology, in the popular Virtex-II fabric, which includes the advanced Active Interconnect(TM) , BlockRAM, and clock management features. This unprecedented level of integration offers systems designers the highest level of performance with the lowest system cost available from any programmable solution. The use of behavioral synthesis technologies enables on-demand architectural synthesis, which allows partitioning for optimal system performance during definition, during debug, and after product shipment. Designers can now get the performance they need without costly and time-consuming re-designs.

About Mentor Graphics Corporation

Mentor Graphics Corporation (Nasdaq: MENT - News) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

About Xilinx Inc.

Xilinx, Inc. (Nasdaq: XLNX - News) is the worldwide leader in programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.

Mentor Graphics, Model Technology, ModelSim and Seamless are registered trademarks of Mentor Graphics Corporation. C-Bridge and Co-Verification Environment are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

     Mentor Graphics
     Wendy Slocum, 503/685-1145
     wendy_slocum@mentor.com
     or
     Weber Shandwick Worldwide
     Jeremiah Glodoveza, 415/352-2628 ext. 136
     jglodoveza@webershandwick.com
     or
     Xilinx, Inc.
     Ann Duft, 408/879-4726
     ann.duft@xilinx.com